1. Technical Field
The embodiments described herein relate to a semiconductor device, and more particularly, to an electrostatic discharge circuit of a semiconductor device.
2. Related Art
In general, in order to prevent an internal circuit in a semiconductor device from being damaged by an electrostatic current, an electrostatic discharge circuit is provided between a pad and the internal circuit.
As semiconductor devices become highly integrated and operate at high speeds, the thickness of the gate oxide layer of the elements formed in the internal circuit of the semiconductor device gradually decreases. Accordingly, a thin gate oxide layer may be easily damaged even by a low voltage. Thus, as a difference between the operation voltage of the internal circuit and a breakdown voltage that damages the gate oxide layer formed in the internal circuit decreases, it is difficult to design an electrostatic discharge circuit such that an operation margin can be secured in consideration of static electricity.
FIG. 1 is a schematic circuit diagram of a conventional electrostatic discharge circuit. In FIG. 1, the electrostatic discharge circuit 1 includes an NMOS transistor type diode N1, a PMOS transistor type diode P1, a charged device model (CDM) resistor R2, a CDM NMOS transistor type diode N2, a capacitor C1, a resistor R1, and an NMOS transistor N3 all disposed between an input/output pad (IO) 10 and an internal circuit, such as an input buffer 16.
In the electrostatic discharge circuit 1, when positive static electricity is introduced through the input/output pad 10 and is discharged through a ground voltage pad VSS 14, the PMOS transistor type diode P1 operates as a parasitic diode and transmits the positive static electricity to a power voltage line 17. If the voltage generated at the resistor R1 by the initial alternate current component of the static electricity that passes through the capacitor C1 is higher than the threshold voltage of the NMOS transistor N3, then the NMOS transistor N3 is turned ON and provides a discharge path between the power voltage line 17 and a ground voltage line 19, and the positive static electricity is discharged to the ground voltage pad 14 through the NMOS transistor N3.
When negative static electricity is introduced through the input/output pad 10, the NMOS transistor type diode N1 operates as a parasitic diode and is turned ON. Accordingly, if the voltage generated at the resistor R1 by the initial alternate current component of the static electricity that passes through the capacitor C1 is higher than the threshold voltage of the NMOS transistor N3, then the NMOS transistor N3 is turned ON to provide a discharge path between the power voltage line 17 and the ground voltage line 19, and discharges the negative static electricity. Here, the reference numeral 12 designates a power voltage pad VCC.
While the static electricity introduced through the input/output pad 10 is discharged, in order to prevent the voltage supplied to the input/output pad 10 from increasing and the input buffer 16 as the internal circuit from being damaged, the CMD resistor R2 and the CMD NMOS transistor type diode N2 are provided. The CMD resistor R2 has large resistance value to prevent an electrostatic current from being applied to the input buffer 16, and the CMD NMOS transistor type diode N2 discharges the static electricity that has passed through the CMD resistor R2 not to be transmitted to the input buffer 16.
An operation voltage for driving the electrostatic discharge circuit 1 is substantially high. For example, the NMOS transistor N3, the NMOS transistor type diode N1, and the PMOS transistor type diode P1 have turn-ON voltages of about 6.2V, 8.3V and 8.1V, respectively. Thus, the gate oxide layer of the input buffer 16 is likely to experience breakdown before the static electricity can be discharged. Furthermore, since the electrostatic discharge circuit 1 must be provided for each input/output pad 10, an overall size of a semiconductor device increases due to the presence of the electrostatic discharge circuit 1.